The present invention relates to a logic analyzer for testing a logic circuit such as a microcomputer.
For instance, in the case where a logic circuit employing a microcomputer is tested by a conventional logic analyzer of this kind as to whether algorithmic operation of the microcomputer, i.e. software works correctly or not, a check is made to see how each step of a program works. In this case, an address for reading out an instruction of the program, the instruction and various data states are input from the logic circuit under test into the logic analyzer, for example, for each address and are displayed. Accordingly, the data loading interval is usually not fixed. Such a test is called a state analysis.
On the other hand, in the case of checking how hardware of the logic circuit operates, the logic analyzer reads the outputs from the logic circuit under test at equal intervals and checks what waveforms they take. This is called a timing analysis.
Conventionally, since the results of the state and the timing analysis are individually displayed, it is difficult to precisely recognize their interrelationships. For the same reason, the prior art logic analyzer does not permit a correct recognition of the results of a plurality of state analyses.
Such conventional logic analyzers are disclosed, for instance, in U.S. Pat. Nos. 4,425,643 and 4,434,485 and U.S. patent applications Ser. Nos. 719,154 (filed on Apr. 2, 1985), 737,466 (filed on May 24, 1985) and 739,467 (filed on May 24, 1985). As shown in FIG. 1, a state analysis section 10 is supplied at an input port 11 with first input data from a logic circuit under test. The first input data is loaded as set logic levels into a temporary memory 13 via a level converter 12 for removing analog components as required. Clock pulses synchronized with those of the first input data to the input port 11 and qualifiers indicating change portions of the data are applied to an input port 14. The input external clock pulses synchronized with the data and the qualifiers are similarly converted by a level converter 15 to logic levels for input into a sampling clock generator 16. The sampling clock generator 16 creates sampling clock pulses 17 corresponding to the change portions of the first input data. By the sampling clock pulses 17, the data from the level converter 12 is loaded into the temporary memory 13. For instance, the first input data to the input port 11, the clock pulses synchronized therewith and the qualifiers are such as shown in FIGS. 2A, B and C, respectively, and the sampling clock pulses have a one-to-one correspondence to the first input data, as depicted in FIG. 2D.
The output of the temporary memory 13 is applied to a data memory 18 and a trigger detector 19. The sampling clock pulses 17 are provided to an address counter 21 wherein they are counted. Upon each occurrence of the sampling pulses 17, the data from the temporary memory 13 is written into the data memory 18 which is addressed by the count value of the address counter 21. Incidentally, the address of the address counter 21 is updated after the write is effected in the data memory 18. The address counter 21 and the data memory 18 have addresses of the same number, and when the address counter 21 overflows, the write is effected again in the data memory 18 starting at the zero address. In this way, the data memory 18 is successively supplied with the first input data from the input port 11.
On the other hand, the trigger detector 19 has set therein trigger data, and when the input data from the temporary memory 13 matches the set trigger data, a delay counter 22 serving as a delay means starts to count the sampling clock pulses 17. When having counted a set value, the delay counter 22 overflows, that is, yields a delayed output, by which the address counter 21 is stopped from counting, that is, the data input to the data memory 18 is stopped. Thus input data which precedes and follows the same data as the set data (the trigger data) are loaded into the data memory 18.
A timing analysis section 23 is supplied with second input data from a second data input port 24. The second input data is converted by a level converter 25 to a logic level and then input into a temporary memory 26. The write in the temporary memory 26 is effected by an internal sampling clock. That is, the second input data from the level converter 25 is loaded into the temporary memory 26 by sampling clock pulses 28 of a fixed frequency which is available from a sampling clock generator 27. The sampling clock pulses 28 are supplied as well to an address counter 29, by which they are counted. The output of the temporary memory 26 is provided to a data memory 31 and a trigger detector 32. Upon each occurrence of the sampling clock 28, the output of the temporary memory 26 is stored in the data memory 31 which is addressed according to the count value of the address counter 29. The trigger detector 32 detects agreement between its set trigger data and the output of the temporary memory 26. When they match, a delay counter 33 as a delay means starts its operation to count the sampling clock pulses 28. Having counted clock pulses of a number corresponding to a preset delay, the delay counter 33 overflows, that is, produces an output, by which the counting operation of the address counter 29 is stopped.
A control section 34, which is equipped with a microcomputer, for instance, is connected via an interface bus 35 with the data memories 18 and 31, the trigger detectors 19 and 32, the address counters 21 and 29 and the delay counters 22 and 33. The control section 34 is able to set data to be triggered (trigger data) in the trigger detectors 19 and 32, to read out the stored contents of the data memories 18 and 31 controlling the address counters 21 and 29 and to set delay data in the delay counters 22 and 33. The trigger data and delay data are entered through a keyboard (input means) 36, and they are set in the trigger detectors and the delay counters under control of the control section 34. The stored contents of the data memories 18 and 31 can be displayed on a display device 37.
With the above arrangement and operation, the first and second input data before and after the detection of the set trigger data of the trigger detectors 19 and 32 are stored in the data memories 18 and 31, and either one of the data is displayed on the display device 27. For example, in the case of displaying the stored contents of the data memory 18, data indicating various states of program are displayed in the respective lines on a display screen 37a, the trigger data set in the trigger detector 19, that is, the trigger position is indicated by a lateral marker 38 and the states before and after the preset trigger data, for example, steps of the program are sequentially displayed, as shown in FIG. 3A.
The stored contents of the data memory 31 in the timing analysis section 23 are displayed on the display screen 37a of the display device 37, as depicted in FIG. 3B. The states of outputs of the logic circuit (logic waveforms) are displayed with the lateral direction as the time axis, and the logic outputs of respective parts are arranged in the vertical direction. In this instance, the trigger data detected by the trigger detector 32 corresponds to a set of those logic states on a broken line marker 39 in the vertical direction, that is, in a direction perpendicular to the time axis.
Conventionally, the data of the data memory 18 in the state analysis section 10 and the data of the data memory 31 in the timing analysis section 23 are selectively displayed on the display device 37, one at a time through manipulation of the keyboard 36, as described above.
If corresponding trigger data are preset in the respective trigger detectors 29 and 32, then the first input data to the input port 11 and the second input data to the input port 24 will correspond to each other at the time of trigger generation by the trigger detectors 29 and 32. Accordingly, the status (data) indicated by the trigger marker 38 in the data display of the state analysis section 10 and the data indicated by the trigger marker 39 in the display of the timing analysis section 23 can be correlated to each other. However, the state analysis section 10 inputs data, for example, upon each change in the address or status data, as described previously, and the time axis in the vertical direction in FIG. 3A is not always graduated at regular intervals, in other words, the time intervals between data displayed at adjacent lines are usually not fixed. The display in FIG. 3A merely indicates data in order of occurrence not in terms of time.
In the display for the data in the timing analysis section 23, shown in FIG. 3B, respective parts of the display on the time axis, i.e. in the horizontal direction, correspond to data sampled at equal time intervals, so that the position of the trigger marker 39 corresponds to the point at which its data was input. Therefore, even if provision is made for making the trigger markers 38 and 39 indicate the same point of time, respective data for the state analysis and the timing analysis, occurring before and after the trigger markers, cannot be made to correspond in terms of time. Thus it is difficult to check the interrelationships of the both displays.
Sometimes the data displayed on the display device 37 is selectively read out specifying a desired place with a cursor. In the case where the state analysis section 10 and the timing analysis section 23 are both provided, or where two state analysis sections are provided, it would be very convenient if such a desired part of data of one analysis section specified by the cursor and that part of data of the other analysis section corresponding thereto in time could be displayed simultaneously. But the conventional logic analyzer has no such capability.
Furthermore, it would also be very convenient if such corresponding data of the two analysis sections could always be displayed together during scrolling, but this function has not been implemented yet.